The present disclosure relates in general to receivers for wireless communication and in particular to a continuous-time delta-sigma modulator and a signal processing system applied to audio equipment and medical measuring instruments.
FIG. 1 shows a basic structure of a delta-sigma modulator.
The delta-sigma modulator 1 in FIG. 1 is made up of a filter FLT, a quantifier Quan, and a digital-analog converter DAC1.
The delta-sigma modulator 1 constitutes a feedback modulator that includes a digital-analog (DA) converter DAC1 and a filter FLT for filtering the quantification noise generated by the quantifier Quan within a signal band (i.e., a band frequency lower than the sampling frequency of the quantifier) in order to improve signal-to-noise ratio (SNR).
If the filter FLT is a continuous-time type, the modulator acts as a continuous-time delta-sigma modulator; if the filter FLT is a discrete-time type, the modulator serves as a discrete-time delta-sigma modulator. The filter FLT is designed to have a high gain within the signal band so as to balance quantization noise attenuation with stability.
FIG. 2 shows a typical structure of a delta-sigma modulator having a zero-order feedback path.
In the continuous-time delta-sigma modulator, a delay in a feedback signal caused by the quantifier Quan and digital-analog converter DAC1 is called an excess loop delay (ELD). This delay, if taking place, can degrade primarily the stability of the delta-sigma modulator.
In order to avoid destabilization, the zero-order feedback path Path0 including a digital-analog converter DAC0 and a weight k0 is generally added as shown in FIG. 2. This technique is used to make up for the signal delay attributable to the loop delay (ELD) and to reinforce stability.
FIGS. 3 and 4 are block diagrams showing typical structures of ordinary continuous-time 3rd-order delta-sigma modulators. The delta-sigma modulator 1B in FIG. 3 is called a feedback modulator, and the delta-sigma modulator 1C in FIG. 4 is called a feed-forward modulator. Each of the modulators is furnished with the zero-order feedback path Path0.
It should be noted that where an adder is positioned upstream of an integrator such as an adder ADD1 and an integrator INT1 in FIG. 3, both are generally formed as integral parts when made into a circuit.
On the other hand, where an adder or adders are followed immediately downstream by a quantifier such as an adder ADDQ in FIG. 3 or adders ADD1 and ADDQ in FIG. 4 followed immediately downstream by a quantifier Quan, it is difficult to form these parts integrally.
If the modulator is implemented using an analog adder such as one shown in FIG. 5 (ANLADD) having an operational transconductance amplifier (OTA) 1 and resistive elements R1, R2 and Radd, the circuit scale and power consumption can grow.
Thus if a filter FLT2D is structured using a differentiator DIFF1 as shown in FIG. 6, the adder ADD1 in FIG. 4 can be moved to immediately upstream of a final-stage integrator INT3 (i.e., input side of the integrator INT3) without change in the filter characteristics.
The adder ADDQ immediately upstream of the remaining quantifier Quan is needed to additionally provide the zero-order feedback path Path0. This adder, too, can be moved to immediately upstream of the final-stage integrator INT3 using the differentiator likewise.
FIGS. 7 and 8 show typical structures of the modulators without the adder positioned upstream of the quantifier as indicated in FIGS. 3 and 6.
FIG. 7 shows a typical structure of a feedback type continuous-time 3rd-order delta-sigma modulator that eliminates the adder upstream of the quantifier.
FIG. 8 shows a typical structure of a feed-forward type continuous-time 3rd-order delta-sigma modulator that also eliminates the adder upstream of the quantifier.
FIG. 9 shows how to implement an adder ADD1, an integrator INT3, differentiators DIFF0 and DIFF1, and weights k0, k1, k2 and k3 making up a portion of the modulator in FIG. 8.
The portion in FIG. 8 that contains the adder ADD1, integrator INT3, differentiators DIFF0 and DIFF1, and weights k0, k1, k2 and k3 is shown implemented by a circuit 2 in FIG. 9 including an operational transconductance amplifier OTA, resistive elements Rk2 and Rk3, and capacitors Ck0, Ck1 and Cint3.
In the circuit 2 of FIG. 9, the integral capacitor Cint3 is charged with the current flowing through the resistive elements Rk2 and Rk3 in a manner corresponding to input voltages V2 and V3, whereby the integral action is implemented.
Meanwhile, the differentiators DIFF0 and DIFF1 in FIG. 8 are implemented using the capacitors Ck0 and Ck1 instead of resistors.
A digital-analog converter DAC0 in FIG. 8 is a line-voltage output type. If the delta-sigma modulator is implemented as a multi-bit output type and the digital-analog converter DAC0 as a parallel DAC arrangement for outputting one LSB, then the capacitor Ck0 in FIG. 9 is arrayed in parallel as well.
The input/output relational expression applicable to the circuit in FIG. 9 is given by the following expression:
                              V          out                =                                                                              C                                      k                    ⁢                                                                                  ⁢                    1                                                                    C                                      int                    ⁢                                                                                  ⁢                    3                                                              ·                              V                1                                      +                                          1                                                      sR                                          k                      ⁢                                                                                          ⁢                      2                                                        ⁢                                      C                                          int                      ⁢                                                                                          ⁢                      3                                                                                  ·                              V                2                                      +                                          1                                                      sR                                          k                      ⁢                                                                                          ⁢                      3                                                        ⁢                                      C                                          int                      ⁢                                                                                          ⁢                      3                                                                                  ·                              V                3                                      +                                                            C                                      k                    ⁢                                                                                  ⁢                    0                                                                    C                                      int                    ⁢                                                                                  ⁢                    3                                                              ·              VDACout                                <          1          >                                    (        1        )            
As can be seen from the expression (1) above, differentiators and integrators constituting a path cancel one another out so that the gain of the path is expressed by a capacity ratio.
Since the variations of the elements of one type within a chip (local variations) are generally smaller than the variations between chips (global variations), the gain determined by the capacity ratio may be implemented with high accuracy.
In this connection, the reader is asked to refer to W. Yang, W. Schofield, H. Shibata, S. Korrapati, A. Shaikh, N. Abaskharoun, D. Ribner, “A 100 mW 10 MHz-BW CT ΔΣ Modulator with 87 dB DR and 91 dBc IMD,” ISSCC Dig. Tech. Papers, pp. 498-499. February 2008 (called the Non-Patent Document 1 hereunder).